Exemplary embodiments relate to continuous spatial correlation for embedded devices on a chip, and more specifically, to making the discrete correlation for the embedded devices into continuous correlations among the devices.
Wafer fabrication trends are dictating the need for direct understanding of across-chip performance variations: increasing lithography complexity resulting in an alphabet soup of design for manufacturing (DFM) products; and the increasing pattern factor variation between the chip active area and scribe monitoring due to greater functional integration at the chip level for microprocessor manufacturers and to the pressure to deliver functional hardware quickly for foundry manufacturers to win business. Many logic houses routinely embed devices (typically ring oscillators) in the active area and route the embedded devices so that they can be tested at final test as part of their yield/diagnostic strategy. These are measured to understand in-die performance variations resulting from across-chip variations (ACV) of semiconductor process: from photo/etch interactions, copper chemical-mechanical polishing (CMP) dishing and erosion, and other process interactions not observed with “scribe” measurements.